1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to the formation of oxide layers to be used between conductive features designed on multiple levels of a semiconductor device.
2. Description of the Related Art
As the demand for faster, smaller, and more densely packed integrated circuit designs continues to increase, design engineers are faced with a greater burden of designing high performance chips at a reasonable cost. Although conventional methods of chip fabrication can be performed at a reasonable cost, they have noticeable limitations as chip dimensions steadily decrease. To illustrate some of the conventional fabrication methods and their associated limitations, reference is now drawn to FIGS. 1A through 1E.
FIG. 1A shows a cross-sectional view of a conventional chip fabrication process where patterned conductive features 12 are fabricated over a semiconductor substrate 10. The patterned conductive features 12 are typically polysilicon gate lines or metal lines. A conventional high density plasma (HDP) oxide 14 is used to fill the gaps between the patterned conductive features 12. The reason for using a conventional HDP oxide 14 is to fill the high aspect ratio gaps. Although conventional HDP oxide 14 works well in filling these gaps, the HDP operation itself causes the formation of oxide pyramids 15 over the patterned conductive features 12. Plasma enhanced chemical vapor deposition (PECVD) oxide 16 is then deposited over the layer of HDP oxide 14. As a result of having the oxide pyramids 15 on top of the patterned conductive features 12, low density oxide seams 18 are created during the formation of the PECVD oxide 16. In general, the low density oxide seams 18 have a slightly less dense characteristic relative to the bulk of the PECVD oxide 16.
FIG. 1B shows the conventional fabrication process of FIG. 1A after an oxide chemical mechanical polishing (CMP) operation has been used to planarize the top surface of the PECVD oxide 16. Unfortunately, indentations 20 are created on the surface of the PECVD oxide 16 due to the low density oxide seams 18. More specifically, because the oxide seams 18 have a less dense characteristic, the chemical used during the CMP operation tends to remove more of this oxide material.
FIG. 1C shows a continuation of the conventional fabrication process of FIG. 1B. A via hole 23 is etched down to a portion of the patterned conductive features 12a. It can be appreciate that via hole 23 is merely for illustration purposes, as thousands or millions of via holes are typically etched at any given interconnect layer. In order to begin filling the via hole, a Titanium (Ti)/Titanium Nitride (TiN) layer 22 is deposited over the wafer. The Ti/TiN layer 22 provides a first layer of conductive material in the via hole 23 (e.g., acts as a glue layer). This requires that the material be deposited over the entire surface of the wafer. In order to finish filling the via hole 23, a tungsten (W) layer 24 is deposited over the wafer. The W layer 24, thereby, fills the via hole 23 and establishes a conductive via. As shown, the entire wafer surface is coated with conductive material. Unfortunately, the Ti/TiN layer 22 and the W layer 24 also fill the indentations 20 created during the CMP due to the low density oxide seams 18.
FIG. 1D shows a continuation of the conventional fabrication process of FIG. 1C. The top surface has undergone a tungsten chemical mechanical polishing (CMP) in order to smooth the surface and polish away the Ti/TiN layer 22 and the W layer 24. The goal of the tungsten CMP is to leave the top surface of the PECVD oxide 16 layer free of conductive material and expose the metal material of the conductive vias. Unfortunately, after the tungsten CMP, conductive stringers 26 remain due to the Ti/TiN layer 22 and the W layer 24 that filled the indentations 20. As discussed above with reference to FIG. 1C, the indentations 20 are created due to the low density oxide seams 18. Notice that the conductive stringers 26 may extend along the top surface of the wafer.
FIG. 1E shows a continuation of the conventional fabrication process of FIG. 1D. Patterned metallization features 30a and 30b are formed by first depositing a blanket metallization material and then performing conventional photolithography patterning. Because metallization interconnect lines are patterned in many different geometric shapes throughout a layer to complete desired electrical interconnections, the patterned metallization features 30a and 30b may pass over the conductive stringers 26, as shown in FIG. 1E. The problem is that the conductive stringers 26, which are flaws in the fabrication process, cause inappropriate conductive interaction between the patterned metallization features 30a and 30b. When this happens, the functionality of a given integrated circuit design may fail to produce the desired response. As a result, the entire integrated circuit may have to be discarded, which adds a significant amount of cost to the fabrication process and lowers throughput.
In view of the foregoing, what is needed is a method for fabricating integrated circuit designs that avoid the creation of unwanted stringers 26, which cause short circuits and inappropriate electrical responses. There is also a need for an integrated circuit design, which is fabricated to avoid introducing the aforementioned stringers 26.